Electrical & Computer Engineering
Department of Electrical and Computer Engineering
University of California, Santa Barbara
Santa Barbara, CA 93106-9560
tel: (805) 729-1410
fax: (805) 893-3262
Personal web site
Cryogenic Nano-power Thermometer
This 0.25um chip incorporated 288 transistors, resistors and small analog circuits in a Kelvin probe configuration to test a variety of on-chip low-power thermal sensing devices optimized for high sensitivity at 35-45K.
VLSI design and coupled tools development based on systematic and formal approaches as well as heuristic analysis. Processor and controller development for embedded, low power and environmentally challenged applications. Interfacing and sampling-based mixed signal design aimed a high loop bandwidth, extreme low power control.
Low Power Control: This work started one year ago seeks to drastically reduce the power consumption of digital feedback controller which have become ubiquitous in embedded systems used in cars, appliances and portable phones. The essential issue is that control algorithms perform largely repetitive tasks on data that is usually slowly changing, or changing at rates defined by physically limited systems. All current approaches to these systems rely on general purpose or DSP specific computers, neither of which exploit this property. These assumptions are particularly pernicious in the case of MEMS (micro mechanical systems). Scaling of the physical size leads to increasing loop bandwidth requirements making the excess power dissipation even greater. Our first efforts in this line were hardware multi-threaded processors which could exploit the bursty nature of control computations. This effort is multi-disciplinary and includes collaborations with Prof. Roy Smith (Controls), Prof. Tim Sherwood (Architecture), and Prof. Kim Turner (Mechanical Engineering). This work has already lead to a major funding request.
Radiation Hardened VLSI Design: in this work, communication link, routing and storage components are being designed for experiments at the LHC (Large Hadron Collider) at CERN under a DOE contract. This environment is very challenging with dose accumulations of 20-70MRad/yr and design lifetimes of 5-7 years. This is work in collaboration with the UCSB Department of Physics.
Chip to Chip Communications: A high-speed asynchronous communication link is in development for low-power intermittent communication between integrated circuits at the board/system level. Using a simple self-timed protocol, the method uses pulse-logic on paired SLVDS signals to robustly link chips at multi-GHz rates without PLL, DLL or critical timing/clock recovery requirements. Energy per bit is within 60% of equivalent speed conventional links, but with greatly reduced linearity and inter-symbol modulation constraints. Most importantly, the link needs no setup or keep-alive signalling, greatly lowering the actual link energy costs.
PBS+/TDL: is a digital system design language based on a notion of latency tolerant structures in which correctness is conserved for all implementations of the spec -- but performance is subject to the design decisions. Based loosely on synchronous event languages like Bluespec and on our own PBS+ (regular expression) protocol specification, TDL allows very concise description of digital computing systems -- for example a few pages of TDL create a synthesizable Verilog spec for a multi-threaded AVR processor, which synthesizes to a high performance (400MHz+ in 0.15um) design nearly automatically. We are actively developing elastic clocking for this language to further enhance performance and lower the power requirements.
Professor Brewer joined the UCSB faculty in 1988, he was formerly a consulting engineer and a senior engineer at Northrop Corp. Advanced Technology Division. His research interests are in VLSI design as well as computer aided design tools and analysis. Recent work is in the development of a family of specialized microprocessors for low-power/ high-performance embedded closed loop control. This work spans mixed signal design at the sensor and actuator interfaces to multi-threaded digital system design in the digital processing parts. By using multi-threading and other architectural tricks, substantial power reduction and performance improvement is possible when compared to commodity DSP processors for this problem. A related issue in this domain is fault tolerance in the controller as such controllers are often deployed in nasty environments such as automobiles or space applications.
He also works on formal techniques for design representation and related software tools as well as generic chip feasibility and design analysis which are done on a consulting basis. An example of the formal work is the processor designs above, which are specified in TDL, a very high level language which provides latency tolerance as well as eliminating a large number of critical paths in the resulting core.
- California Nanosystems Institute
- Allosphere Steering Committee (Media Technology)