UCSB Engineering

Timothy Sherwood


Computer Science

Timothy Sherwood


Department of Computer Science
University of California
Santa Barbara, CA 93106-5110


Personal web site

Research Description

Professor Sherwood's research is in the area of computer architecture, specifically in the development of novel high throughput hardware and software methods by which systems can be monitored and analyzed. Such techniques provide a powerful new way to inspect and control the digital world --- they shed light on performance anomalies, uncover software bugs, and help secure critical systems against attack. His students work across all layers of the hardware/software stack, from circuits to software application, and his prior work on phase analysis has seen adoption by many major manufactures to help them design and analyze their processors.

Research Groups


Before joining UCSB in 2003, Sherwood received his B.S from UC Davis (1998) and his M.S. and Ph.D. from UC San Diego (2003) where he worked with Professor Brad Calder. In his short time with UCSB, Professor Sherwood has received the 3 consecutive IEEE Micro Top Pick Awards for novel contributions significant to industry, and an NSF CAREER award in 2005. His prior work on Program Phase Analysis methods (a technique for reasoning about and predicting the behavior of programs over time -- a critical step in reducing power consumption) has been cited over 350 times and is now used by Intel, HP, and other industry partners to guide the design of their largest microprocessors.


  • Northrop Grumman Excellence in Teaching Award, 2008
  • IEEE Micro Top Pick, 2006
  • Code Generation and Optimization: Best Paper, 2005
  • IEEE Micro Top Pick, 2005
  • NSF Career Award, 2005
  • IEEE Micro Top Pick, 2004

Selected Publications

See complete list of publications
  • A Case Study of Multi-Threading in the Embedded Space, Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2006, Greg Hoover, Timothy Sherwood, Forrest Brewer, web link
  • A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy, Proceedings of the 43nd Design Automation Conference (DAC), 2006, Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee, web link
  • Bit-Split String-Matching Engines for Intrusion Detection and Prevention, ACM Transactions on Architecture and Code Optimization (TACO), Vol 3 No 1, 2006, Lin Tan, Brett Brotherton, and Timothy Sherwood, web link
  • Introspective 3D Chips, Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2006, Shashidhar Mysore, Banit Agrawal, Sheng-Chih Lin Lin, Navin Srivastava, Kaustav Banerjee and Timothy Sherwood, web link
  • Leakage Power Reduction of Embedded Memories on FPGAs Through Location Assignment, Proceedings of the 43nd Design Automation Conference (DAC), 2006, Yan Meng, Timothy Sherwood, and Ryan Kastner, web link
  • Policy-Driven Memory Protection for Reconfigurable Hardware, Proceedings of the European Symposium on Research in Computer Security (ESORICS), 2006, Ted Huffmire, Shreyas Prasad, Tim Sherwood and Ryan Kastner
  • Virtually Pipelined Network Memory, International Symposium on Microarchitecture (Micro), 2006, Banit Agrawal and Timothy Sherwood, web link
  • Automatically Characterizing Large Scale Program Behavior, Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2002, Timothy Sherwood, Erez Perelman, Greg Hamerly and Brad Calder, web link