UCSB Engineering

Patrick Yue

Associate Professor & Associate Director of Computer Engineering

Contacts

UCSB Department of Electrical Engineering
5159 Harold Frank Hall
Santa Barbara, CA 93106

tel: 805-893-7825
fax: 805-893-3262
cpyue@ece.ucsb.edu

Personal web site

Research Description

Current and past projects: ~~~ (1) High-Performance RF Design Based on Technology-Independent, Scalable Sub-Circuit Cells ~~~ (2) Very Low Power, Adaptive Equalizer for High-Speed Communications ~~~ (3) In-scribe-line, Wireless Test Circuitries for On-wafer Process Variation Monitoring ~~~ (4) Millimeter-Wave MIMO: A New Architecture For
Integrated 10-40 Gigabit Wireless/Optical Hybrid Networks ~~~ (5) Millimeter-Wave CMOS Computer-Aided Design ~~~ (6) Self-Contained Sensor Skin for Highway Bridge Monitoring

Research Groups

• High-Speed Silicon Lab

Biography

Prof. Patrick Yue received his Ph.D. in EE from Stanford in 1998. He is currently an Associate Professor in ECE Department and the Associate Director of Computer Engineering Program at the University of California Santa Barbara. He is an Adjunct Professor in the ECE Department of Carnegie Mellon University, Pittsburgh, PA and in the Institute of Microelectronics at the Chinese Academy of Sciences, Beijing, China. His current interests include high-speed CMOS wireless and wireline IC design, cell-based RF/mm-wave modeling and design methodology, and integrated biomedical sensors. From 2003-2006, he was with Carnegie Mellon University as an Assistant Professor in ECE. From 1998-2002, he co-founded Atheros Communications and contributed to the development of the first 802.11a CMOS RF transceiver for high-volume production which ignited the proliferation of Wi-Fi technology. While working in the industry, Prof. Yue held the position of a Consulting Assistant Professor in Electrical Engineering at Stanford University between 2001 and 2003. Prof. Yue remains active in consulting for IC design companies and currently serves on the advisory boards of several semiconductor startups in the U.S. and China. Prof. Yue has contributed to more than fifty peer-reviewed technical papers and two book chapters. He currently holds thirteen U.S. patents, majority of which are utilized in commercial products. He was the co-recipient of the 2003 International Solid-State Circuits Conference (ISSCC) Best Student Paper Award. His 1998 paper “On-chip spiral inductors with patterned ground shields for Si-based RF ICs” is among the most cited articles in the history of the IEEE Journal of Solid-State Circuits according Thomson ISI. He has served on the technical program committees of the IEEE RFIC Symposium, A-SSCC, VLSI-DAT, ISLPED, and CSICS. He has been a member of the IEEE Electron Devices Society VLSI Technology and Circuits Committee and a Senior Member of IEEE since 2005.

Awards/Honors

• Best Student Paper, IEEE International Solid-State Circuits Conference (ISSCC), 2003
• All-Time Top Cited Paper in IEEE Journal of Solid-State Circuits (JSSC), 1998

Selected Publications

• A two-tone test method for continuous-time adaptive equalizers, Design, Automation and Test in Europe Conference and Exposition (DATE), 2007, 1283-1288, Dongwoo Hong, Shadi Saberi, Kwang-Ting Cheng, C. Patrick Yue
• Low-Power, Parallel Interface with Continuous-Time Adaptive Passive Equalizer and Crosstalk Cancellation, Design of High-Speed Communications Circuits, 2006, 459-476, C.P. Yue, J. Park, R. Sun, L.R. Carley, and F. O’mahony
• Analysis and Synthesis of On-Chip Spiral Inductors, IEEE Transactions on Electron Devices, Vol. 52, No.2, 2005, 176-182, N.A. Talwalkar, C.P. Yue, and S.S. Wong
• Experimental Evidence for Gyromagnetic Damping in Magnetic Heads Determined by Impedance Measurements up to 9 GHz, IEEE Transactions on Magnetics, Vol. 41, No. 10, 2005, 2923-2925, A. Kaya, C.P. Yue, and J.A. Bain
• Scalability of RF CMOS (Invited), IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Digest of Papers, 2005, 53-56, C.P. Yue and S.S. Wong
• Extraction and Applications of On-Chip Interconnect Inductance (Invited), Proceedings of the 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSSICT), 2004, 141-146, S.S. Wong, S.-Y. Kim, C.P. Yue, R. Chang, F. O'Mahony
• Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications, IEEE Journal of Solid-State Circuits, Vol. 39, No. 6, 2004, 863-870, N.A. Talwalkar, C.P. Yue, H. Gan, and S.S. Wong
• Modeling and optimization of substrate resistance for RF-CMOS, IEEE Transactions on Electron Devices, Vol. 51, No.3, 2004, 421-426, R.T. Chang, M.-T. Yang, P.P.C. Ho, Y.-J. Wang, Y.-T. Chia, B.-K. Liew, C.P. Yue, and S.S. Wong
• A 10-GHz Global Clock Distribution Using Coupled Standing-Wave Oscillators, IEEE Journal of Solid-State Circuits, Vol. 38, No. 11, 2003, 1813-1820, F. O'Mahony, C.P. Yue, M.A. Horowitz, S.S. Wong
• Low-Latency Modulated Signaling over On-Chip Electrical Interconnects, IEEE Journal of Solid-State Circuits, Vol.38, No.5, 2003, 834-838, R.T. Chang, N. Talwalkar, C.P. Yue, and S.S. Wong