UCSB Engineering

Patrick Yue

Professor

Contacts

UCSB Department of Electrical Engineering
5159 Harold Frank Hall
Santa Barbara, CA 93106

tel: 805-893-7825
fax: 805-893-3262
cpyue@ece.ucsb.edu

Personal web site

Research Description

Current and past projects: (1) Cell-Based RF Design in Scaled CMOS Technologies (2) Very Low Power, Adaptive Equalizer for High-Speed I/O's (3) On-wafer Wireless Testing (4) Low-power Wireless Bio-sensors (5) Fast-settling PLL's

Research Groups

• High-Speed Silicon Lab

Biography

Prof. C. Patrick Yue received his BS in EE from UT Austin in 1992 with highest honor and his MS in EE and PhD from Stanford in 1994 and 1998, respectively. He is currently a Professor in Electrical and Computer Engineering at the University of California, Santa Barbara (UCSB). Starting in July 2010, he is on sabbatical leave to the Hong Kong University of Science and Technology as a Visiting Professor in Electronic and Computer Engineering. His research interests include high-speed wireless and wireline circuit design, RF and mm-wave device modeling, and energy-efficient interface circuits for sensors. Based on his PhD work at Stanford, in 1998, he co-founded Atheros Communications (NSDQ: ATHR) and contributed to the deployment of the world’s first 802.11a 5-GHz CMOS RF transceiver. In 2002, he joined anther silicon valley startup Aeluros (acquired by Netlogic, NSDQ: NETL) to develop 10-Gbps serial link products focusing on signal integrity issues at the chip, package and PCB interface. After five years of industry experience, Dr. Yue returned to academia to join Carnegie Mellon University, Pittsburgh, PA, where he taught between 2003 and 2006 as an Assistant Professor in Electrical and Computer Engineering. In 2006, he moved back to CA and started teaching at UCSB. Prof. Yue remains passionate about technology entrepreneurship and is an active advisor to a number of IC startups based in China. Prof. Yue has contributed to more than 70 peer-reviewed technical papers and two book chapters. He currently holds 13 US patents of which most are employed in actual products. He was a co-recipient of the 2003 International Solid-State Circuits Conference (ISSCC) Best Student Paper Award and the author of one of the all-time most cited paper in IEEE Journal of Solid-State Circuits. He has served on various conference committees including A-SSCC, ISLPED, RFIC Symposium and VLSI-DAT. He has been a member of the IEEE Electron Devices Society VLSI Technology and Circuits Committee and a Senior Member of IEEE since 2005.

Awards/Honors

• Best Student Paper, IEEE International Solid-State Circuits Conference (ISSCC), 2003
• All-Time Top Cited Paper in IEEE Journal of Solid-State Circuits (JSSC), 1998

Selected Publications

• A two-tone test method for continuous-time adaptive equalizers, Design, Automation and Test in Europe Conference and Exposition (DATE), 2007, 1283-1288, Dongwoo Hong, Shadi Saberi, Kwang-Ting Cheng, C. Patrick Yue
• Low-Power, Parallel Interface with Continuous-Time Adaptive Passive Equalizer and Crosstalk Cancellation, Design of High-Speed Communications Circuits, 2006, 459-476, C.P. Yue, J. Park, R. Sun, L.R. Carley, and F. O’mahony
• Analysis and Synthesis of On-Chip Spiral Inductors, IEEE Transactions on Electron Devices, Vol. 52, No.2, 2005, 176-182, N.A. Talwalkar, C.P. Yue, and S.S. Wong
• Experimental Evidence for Gyromagnetic Damping in Magnetic Heads Determined by Impedance Measurements up to 9 GHz, IEEE Transactions on Magnetics, Vol. 41, No. 10, 2005, 2923-2925, A. Kaya, C.P. Yue, and J.A. Bain
• Scalability of RF CMOS (Invited), IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Digest of Papers, 2005, 53-56, C.P. Yue and S.S. Wong
• Extraction and Applications of On-Chip Interconnect Inductance (Invited), Proceedings of the 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSSICT), 2004, 141-146, S.S. Wong, S.-Y. Kim, C.P. Yue, R. Chang, F. O'Mahony
• Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications, IEEE Journal of Solid-State Circuits, Vol. 39, No. 6, 2004, 863-870, N.A. Talwalkar, C.P. Yue, H. Gan, and S.S. Wong
• Modeling and optimization of substrate resistance for RF-CMOS, IEEE Transactions on Electron Devices, Vol. 51, No.3, 2004, 421-426, R.T. Chang, M.-T. Yang, P.P.C. Ho, Y.-J. Wang, Y.-T. Chia, B.-K. Liew, C.P. Yue, and S.S. Wong
• A 10-GHz Global Clock Distribution Using Coupled Standing-Wave Oscillators, IEEE Journal of Solid-State Circuits, Vol. 38, No. 11, 2003, 1813-1820, F. O'Mahony, C.P. Yue, M.A. Horowitz, S.S. Wong
• Low-Latency Modulated Signaling over On-Chip Electrical Interconnects, IEEE Journal of Solid-State Circuits, Vol.38, No.5, 2003, 834-838, R.T. Chang, N. Talwalkar, C.P. Yue, and S.S. Wong