UCSB Engineering

Kaustav Banerjee

Professor

Electrical & Computer Engineering

Kaustav Banerjee

Contacts

Department of Electrical and Computer Engineering
4151 Harold Frank Hall, University of California
Santa Barbara, CA 93106-9560

tel: (805) 893-3337
fax: (805) 893-3262
kaustav@ece.ucsb.edu

Personal web site

Carbon Nanomaterials for Next-Generation High-Performance and Energy-Efficient "Green" Electronics

Carbon Nanomaterials for Next-Generation High-Performance and Energy-Efficient "Green" Electronics

Two feasible ultra high-density capacitive energy storage concepts from, "Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects’’ by H. Li, C. Xu, N. Srivastava and K. Banerjee, IEEE TED, Vol. 56, No. 9, pp. 1799-1821, 2009.

Research Description

Work in the Nanoelectronics Research Laboratory (NRL) at UCSB focuses on the following central themes:
(i) Physics, technology, and applications of graphene based nanomaterials.
(ii) Exploration of innovative techniques and methods for overcoming fundamental limitations in next-generation integrated electronics, photovoltaics/photonics, and bioelectronics.
(iii) Circuits and systems issues in emerging nanoelectronics including 3-D ICs.

Research Groups

Biography

Kaustav Banerjee is a Professor of Electrical and Computer Engineering and Director of the Nanoelectronics Research Lab at UC Santa Barbara. He is also an Affiliated Faculty with the California NanoSystems Institute (CNSI) and the Institute for Energy Efficiency (IEE) at UCSB. Initially trained as a physicist, he received the Ph.D. degree in Electrical Engineering and Computer Sciences (with minors in Physics and Materials Science) from the University of California, Berkeley, in 1999, working with Prof. Chenming Hu. His research interests include nanometer-scale issues in CMOS VLSI as well as circuits and systems issues in emerging nanoelectronics. He is currently involved in exploring the physics, technology, and applications of carbon nanomaterials for next-generation green electronics. Prof. Banerjee has made seminal contributions in almost every area he has worked on, and his technical ideas and innovations have seen wide-spread proliferation both in the industry and academia as exemplified by his h-index of 40 (from Google Scholar) as of Jan 2012. His doctoral research at Berkeley and subsequent work at Stanford on thermal issues in integrated circuits played a pioneering role in introducing the concept of “thermal integrity”, which set the foundation for Gradient Design Automation, the first company to introduce temperature-aware IC design technology in the Electronic Design Automation Industry. He has also made a number of key contributions in the area of nanoscale IC interconnects and innovative interconnect solutions including 3-D ICs and carbon-based interconnects, which have helped shape the semiconductor industry's R&D efforts in those areas.

Affiliations

  • Computer Engineering
  • California NanoSystems Institute (CNSI)
  • Institute for Energy Efficiency (IEE)

Awards/Honors

  • Elected as IEEE Fellow, 2011
  • Friedrich Wilhelm Bessel Research Award, Alexander von Humboldt Foundation, Germany, 2011
  • Keynote Speaker, ACM TAU, Santa Barbara, CA, 2011
  • Keynote Speaker, IEEE EDAPS, Hangzhou, China, 2011
  • Research Award, Electrostatic Discharge Association (ESDA), 2011
  • Plenary Speaker, Ultimate Integration on Silicon (ULIS), Glasgow, Scotland, 2010
  • Reserach Award, ESD FORUM e.V., Germany, 2010
  • Visiting Professorship, Tokyo Institute of Technology, Japan, 2010
  • Invited Speaker, Global-COE International Symposium on Silicon Nano Devices in 2030: Prospects by World's Leading Scientists, Tokyo, 2009
  • Keynote Speaker, International Electrostatic Discharge Workshop (IEW), Lake Tahoe, CA, 2009
  • Agilent Foundation Research Award, 2008
  • Distinguished Lecturer Award, IEEE Electron Devices Society, 2008
  • Finalist, IEEE/ACM William J. McCalla ICCAD Best Paper Award, 2008
  • IBM Faculty Award, 2008
  • Keynote Speaker, 12th IEEE Signal Propagation on Interconnects, Avignon, France, 2008
  • IEEE-Micro Top Picks Award, 2006
  • Best Paper Nominee, IEEE International Symposium on Low Power Electronic Design (ISLPED), 2005
  • Outstanding Student Paper Award, 22nd VLSI Multilevel Interconnection Conference, 2005
  • Recognized as Visionary behind Silicon Valley Startup “Gradient Design Automation”, 2005
  • Research Award, Electrostatic Discharge Association (ESDA), 2005
  • ACM SIGDA Outstanding New Faculty Award, 2004
  • Elected as Senior Member of IEEE, 2003
  • First Prize, UC Davis Business Plan Competition, 2002
  • Runner Up, Stanford University Business Plan Competition, 2002
  • Best Paper Award, IEEE/ACM Design Automation Conference (DAC), 2001

Selected Publications

See complete list of publications
  • High-Frequency Behavior of Graphene-Based Interconnects—Part I: Impedance Modeling, Transactions on Electron Devices, Vol. 58, No. 3, 2011, pp. 843-852, Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee, web link
  • High-Frequency Behavior of Graphene-Based Interconnects—Part II: Impedance Analysis and Implications for Inductor Design, IEEE Transactions on Electron Devices, Vol. 58, No. 3, 2011, pp. 853-859, Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee, web link
  • Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs, IEEE Design and Test of Computers, Special Issue on Emerging Interconnect Technologies for Gigascale Integration, July/August, 2010, pp. 20-31, Hong Li, Chuan Xu, and Kaustav Banerjee, web link
  • Compact AC Modeling and Performance Analysis of Through-Silicon Vias (TSVs) in 3-D ICs, IEEE Transactions on Electron Devices, Vol. 57, No. 12, 2010, pp. 3405-3417, Chuan Xu, Hong Li, Roberto Suaya and Kaustav Banerjee, web link
  • Electron-hole Duality During Band-to-Band Tunneling Process in Graphene-Nanoribbon Tunnel-Field-Effect Transistors, Applied Physics Letters, 97, No. 26, 2010, p. 263109, Deblina Sarkar, Michael Krall, and Kaustav Banerjee, web link
  • Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part I: Modeling, Analysis, and Experimental Validation, IEEE Transactions on Electron Devices, Vol. 57, No. 10, 2010, pp. 2504-2514, Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee, web link
  • Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multi-layer Conductive Substrate, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 7, 2009, pp. 1047-1060, Navin Srivastava, Roberto Suaya and Kaustav Banerjee, web link
  • Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects, IEEE Transactions on Electron Devices, Vol. 56, No. 9, 2009, pp. 1799-1821, Hong Li, Chuan Xu, Navin Srivastava, and Kaustav Banerjee, web link
  • High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design, IEEE Transactions on Electron Devices, Vol. 56, No. 10, 2009, pp. 2202-2214, Hong Li and Kaustav Banerjee, web link
  • Hybrid NEMS-CMOS Integrated Circuits: A Novel Strategy for Energy-Efficient Designs, IET Transactions on Computers and Digital Techniques—Special Issue on Advances in Nanoelectronics Circuits and Systems, Vol. 3, No. 6, 2009, pp. 593-608, Hamed Dadgour and Kaustav Banerjee, web link
  • Modeling, Analysis and Design of Graphene Nano-Ribbon Interconnects, IEEE Transactions on Electron Devices, Vol. 56, No. 8, 2009, pp. 1567-1578, Chuan Xu, Hong Li, and Kaustav Banerjee, web link
  • On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnections, IEEE Transactions on Nanotechnology, Vol. 8, No. 4, 2009, pp. 542-559, Navin Srivastava, Hong Li, Franz Kreupl, and Kaustav Banerjee, web link
  • A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs, IEEE Transactions on Electron Devices, Vol. 49, No. 11, 2002, 2001-2007, Kaustav Banerjee and Amit Mehrotra, web link
  • Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, 2002, pp. 904-915, Kaustav Banerjee and Amit Mehrotra, web link
  • 3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration, Proceedings of the IEEE, Vol. 89, No. 5, 2001, pp. 602-633, Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat, web link
  • Global (Interconnect) Warming, IEEE Circuits and Devices Magazine, No. 9, 2001, pp. 16-32, Kaustav Banerjee and Amit Mehrotra, web link
  • High-Current Failure Model for VLSI Interconnects Under Short-PuIse Stress Conditions, IEEE Electron Device Letters, Vol. 18, No. 9, 1997, pp. 405-407, Kaustav Banerjee, Ajith Amerasekera, Nathan Cheung, and Chenming Hu, web link