Electrical & Computer Engineering
Department of Electrical and Computer Engineering
4151 Harold Frank Hall, University of California
Santa Barbara, CA 93106-9560
tel: (805) 893-3337
fax: (805) 893-3262
Personal web site
Carbon Nanomaterials for Next-Generation High-Performance and Energy-Efficient "Green" Electronics
Two feasible ultra high-density capacitive energy storage concepts from, "Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects’’ by H. Li, C. Xu, N. Srivastava and K. Banerjee, IEEE TED, Vol. 56, No. 9, pp. 1799-1821, 2009.
Work in the Nanoelectronics Research Laboratory (NRL) at UCSB focuses on the following central themes:
(i) Physics, technology, and applications of low-dimensional nanomaterials.
(ii) Exploration of innovative techniques and methods for overcoming fundamental limitations in next-generation integrated electronics, photovoltaics/photonics, and bioelectronics.
(iii) Circuits and systems issues in emerging nanoelectronics including 3-D ICs.
Kaustav Banerjee is Professor of Electrical and Computer Engineering and Director of the Nanoelectronics Research Lab at UC Santa Barbara. He is also an Affiliated Faculty with the California NanoSystems Institute (CNSI) and the Institute for Energy Efficiency (IEE) at UCSB. Initially trained as a physicist, he received the Ph.D. degree in Electrical Engineering and Computer Sciences (with minors in Physics and Materials Science) from the University of California, Berkeley, in 1999, working with Prof. Chenming Hu.
His research interests include nanometer-scale issues in CMOS VLSI as well as emerging nanoelectronics. He is currently involved in exploring the physics, technology, and applications of low-dimensional nanomaterials for next-generation green electronics, photonics and bioelectronics.
Prof. Banerjee has made seminal contributions in almost every area he has worked on, and his technical ideas and innovations have seen wide-spread proliferation both in the industry and academia as exemplified by his h-index of 45 (from Google Scholar) as of June 2013. His doctoral research at Berkeley and subsequent work at Stanford on thermal issues in integrated circuits played a pioneering role in introducing the concept of “thermal integrity”, which set the foundation for Gradient Design Automation, the first company to introduce temperature-aware IC design technology in the Electronic Design Automation Industry. He has also made a number of key contributions in the area of nanoscale IC interconnects and innovative interconnect solutions including 3-D ICs and carbon-based interconnects, which have helped shape the semiconductor industry's R&D efforts in those areas.
- Visiting Professor, Tokyo Institute of Technology, Tokyo, Japan
- Visiting Professor, Universität der Bundeswehr Muenchen, Germany
- Guest Professor, Shanghai Jiao Tong University, Shanghai, China
- Visiting Professor, Nanyang Technological University, Singapore
- Computer Engineering (UCSB)
- California NanoSystems Institute (UCSB)
- Institute for Energy Efficiency (UCSB)
- JSPS Invitation Fellowship, Japan Society for the Promotion of Science, 2013
- Best Paper Award & Best Student Paper Award, 34th EOS/ESD Symposium: For pioneering demonstration of Graphene's ESD robustness, 2012
- IEEE Fellow (elected in Fall 2011), 2012
- Nature Nanotechnology Research Highlights (May Issue): For introducing the Tunnel-FET Biosensor (APL, 100, No. 14, 143108, 2012), 2012
- ESDA Research Grant Award, Electrostatic Discharge Association, 2011, 2005
- Friedrich Wilhelm Bessel Research Award, Alexander von Humboldt Foundation, Germany, 2011
- Distinguished Lecturer Award, IEEE Electron Devices Society, 2008
- IBM Faculty Fellow Award, 2008
- IEEE-Micro Top Picks Award, 2006
- Recognized as Visionary behind Silicon Valley Startup “Gradient Design Automation”, 2005
- ACM SIGDA Outstanding New Faculty Award, 2004
- First Prize, Big Bang! Business Plan Competition, UC Davis Graduate School of Management (as Chief Technology Officer of Gradient Design), 2002
- Runner-up, BASES Challenge 2002, Business Association of Stanford Entrepreneurial Students, Stanford University (as Chief Technology Officer of Gradient Design), 2002
- Best Paper Award, IEEE/ACM Design Automation Conference (DAC), 2001
See complete list of publications
- Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications – Part I: Process Development, IEEE Transactions on Electron Devices, Vol. 60, No. 9, 2013, 2862-2869, Hong Li, Wei Liu, Alan M. Cassell, Franz Kreupl and Kaustav Banerjee, web link
- Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe2 Field-Effect-Transistors, Nano Letters, Vol. 13, No. 5, 2013, 1983-1990, Wei Liu, Jiahao Kang, Deblina Sarkar, Yasin Khatami, Debdeep Jena and Kaustav Banerjee, web link
- Proposal for Tunnel-Field-Effect-Transistor as Ultra-Sensitive and Label-Free Biosensors, Applied Physics Letters, 100, No. 14, 2012, 143108, Deblina Sarkar and Kaustav Banerjee, web link
- High-Frequency Behavior of Graphene-Based Interconnects—Part I: Impedance Modeling, Transactions on Electron Devices, Vol. 58, No. 3, 2011, pp. 843-852, Deblina Sarkar, Chuan Xu, Hong Li, and Kaustav Banerjee, web link
- Synthesis of High-Quality Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition, CARBON, Vol. 49, No. 13, 2011, 4122-4130, Wei Liu, Hong Li, Chuan Xu, Yasin Khatami and Kaustav Banerjee, web link
- Electron-hole Duality During Band-to-Band Tunneling Process in Graphene-Nanoribbon Tunnel-Field-Effect Transistors, Applied Physics Letters, 97, No. 26, 2010, p. 263109, Deblina Sarkar, Michael Krall, and Kaustav Banerjee, web link
- Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors––Part I: Modeling, Analysis, and Experimental Validation, IEEE Transactions on Electron Devices, Vol. 57, No. 10, 2010, pp. 2504-2514, Hamed F. Dadgour, Kazuhiko Endo, Vivek De, and Kaustav Banerjee, web link
- Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status and Prospects, IEEE Transactions on Electron Devices, Vol. 56, No. 9, 2009, pp. 1799-1821, Hong Li, Chuan Xu, Navin Srivastava, and Kaustav Banerjee, web link
- High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design, IEEE Transactions on Electron Devices, Vol. 56, No. 10, 2009, pp. 2202-2214, Hong Li and Kaustav Banerjee, web link
- Modeling, Analysis and Design of Graphene Nano-Ribbon Interconnects, IEEE Transactions on Electron Devices, Vol. 56, No. 8, 2009, pp. 1567-1578, Chuan Xu, Hong Li, and Kaustav Banerjee, web link
- On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnections, IEEE Transactions on Nanotechnology, Vol. 8, No. 4, 2009, pp. 542-559, Navin Srivastava, Hong Li, Franz Kreupl, and Kaustav Banerjee, web link
- A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs, IEEE Transactions on Electron Devices, Vol. 49, No. 11, 2002, 2001-2007, Kaustav Banerjee and Amit Mehrotra, web link
- Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, 2002, pp. 904-915, Kaustav Banerjee and Amit Mehrotra, web link
- 3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration, Proceedings of the IEEE, Vol. 89, No. 5, 2001, pp. 602-633, Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat, web link
- Global (Interconnect) Warming, IEEE Circuits and Devices Magazine, No. 9, 2001, pp. 16-32, Kaustav Banerjee and Amit Mehrotra, web link